Recent questions tagged virtual-memory

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Consider a paged virtual memory system with 32-bit virtual address and 1KB pages. Each PTE requires 32 bits. It is desired to limit the page table size to one ... If the bottom level page table has 2^6 entries how many pages are possible?
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If the executing program size is greater than the existing $RAM$ of a computer, it is still possible to execute the program if the $OS$ supports :multitasking virtual memory paging system none of the above
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Without the TLB, in the paging every data/instruction access requires two memory accessesOne for the page table and one for the data / instruction .Can any one explain it with diagram (if possible)?
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Why logical address and physical address are same in case of compile and load time binding ?In complie time as i have read compiler will generate absoute address ... Logical address can be anything?Why it has ti be same as physical address?
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Assume that a task is divided into four equal-sized segments and that the systembuilds an eight-entry page descriptor table for each segment. Thus, the system has ... as follows(a) 16KB(b)16 bits(c)4GB physical memoryAre my answers correct?
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What is the difference between the functions performed in compile time and functions performed in link time?
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What is the difference between Physical Address, Virtual Address and Absolute Address?
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I.Show the address format for virtual address (18)16 (specify field name and size) that would be used by the system to translate to a physical address and then ... is the address in?What is the byte offset?Is the page in physical memory?
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A computer has a cache, main memory and a hard disk used for virtual memory. If referenced word is in cache, 20 ns are required to access it. If it is in ... 1-cachehit) (Tcache + Memoryhit*TMemory +( 1- Memoryhit) (TMemory+Tsec. memory ) )
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I was watching this video lecture suggested by GO videos playlist and can't get my head around the Page Table Entry(PTE) computationAccording to the video @ ... instructor says it's 1 MillionPlease let me know where im i going wrongThanks
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Consider a virtual memory system with 32-bit virtual addresses and 1 KB pages. Each page table entry requires 32- bits. It is desired to limit the page table size to ... Answer for the first one is 3 and for the second one is 8208 bytes.
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If we say virtual address is 34 bit and we use 3 level page table.12 bits page offset.first level page table =9 bitssecond level page table = 5 ... by second level page and first level page table ?If possible please draw diagram .
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I am trying to understand the difference between the valid-invalid bit and the modify bit in pagingMy current understanding is that the valid invalid ... the locations where these are present?Any other insights are gladly accepted
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The minimum number of page frames that must be allocated to a running process in a virtual memory environment is determined by instruction set architecture .How? pls explain this concept.
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What is the technique that allows one to execute a program which is not entirely in memory called?Demand PagingAuxiliary MemorySecondary MemoryVirtual Memory
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In the question https://gateoverflow.in/490/gate2008-67, why is the formula Number of third level page tables possible= Physical memory size / Size of a third level page tablebeing used to calculate the number of third level page tables?
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I have learned that with run-time address binding, the program can be allocated frames in the physical memory non-contiguously. Also, as described here and here, ... of the segments or separately just as in the case of run-time binding ?
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Consider the following passage to answer questions from Q. Nos. 1 to 6 :Virtual Memory is a technique that allows the execution of processes that maynot be completely in the ... B) 10 page faults(C) 14 page faults (D) 12 page faults
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Suppose that a certain computer with paged virtual memory has $4 KB$ pages, a $32-bit$ byte addressable virtual address space, and a $30-bit$ byte ... basic inverted page table, including page numbers and overhead bits is ________ $bytes$.
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A memory system contians a cache, a primary memory and a secondary memory. The access time of cache is 5ns and it has 80% hit rate. The access time of main memory ... of the hierarchy?(A) 10000ns(B) 50099.5ns(C) 10024ns(D) None of these
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In a two-level virtual memory, the memory access time for main memory, $t_{M}=10^{-8}$ ... , $H$ such that the access efficiency is within $80$ percent of its maximum value?