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Recent questions tagged clock-cycles
328
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0
answers
0
votes
Design a Asynchronous Up counter that start it’s counting from zero and ends at 11 and again starts from zero. Draw the output status of all Flip Flops after every clock. How many clocks are required to reach 11?
M.Zain
328
views
M.Zain
asked
Dec 30, 2022
Digital Logic
digital-logic
clock-cycles
flip-flop
+
–
394
views
1
answers
1
votes
DRDO CSE 2022 Paper 2 | Question: 4
A system $\mathrm{X}$ with $2 \mathrm{~GHz}$ clock speed runs a program in $10$ seconds. We want to build a system $\mathrm{Y}$ to run the same program in ... system $\mathrm{X}$. What should be the clock speed of the system $\mathrm{Y}?$
admin
394
views
admin
asked
Dec 15, 2022
CO and Architecture
drdocse-2022-paper2
co-and-architecture
clock-cycles
5-marks
descriptive
+
–
402
views
1
answers
0
votes
cache memory
Consider a RISC processor with an ideal CPI, where 25% of the total instructions are LOAD and STORE instruction. Time to accessing main memory is 100 clock cycles and ... is 2%, then the effective CPI for the system with the cache is ____.
someshawasthi
402
views
someshawasthi
asked
Nov 17, 2022
CO and Architecture
cache-memory
clock-cycles
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–
234
views
0
answers
0
votes
How many cycle per second are spent on I/O if polling is used with Interrupts?
Manpreet Saluja
234
views
Manpreet Saluja
asked
Nov 7, 2022
Computer Networks
co-and-architecture
clock-cycles
input-output
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–
376
views
1
answers
0
votes
SelfDoubt
During the instruction fetch does the program counter increment in the same clock cycle or it take next clock cycle
someshawasthi
376
views
someshawasthi
asked
Oct 27, 2022
CO and Architecture
co-and-architecture
self-doubt
machine-instruction
clock-cycles
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–
1.2k
views
2
answers
1
votes
GATE Overflow | Mock GATE | Test 1 | Question: 60
A program runs in $20s$ in machine A with a clock speed of $200MHz$. A computer architecture wants to build a machine B which will run this program in $6$ ... this program. What clock rate should be targeted for a best design? (In $MHz$)
Ruturaj Mohanty
1.2k
views
Ruturaj Mohanty
asked
Dec 27, 2018
CO and Architecture
go-mockgate-1
numerical-answers
clock-cycles
clock-frequency
co-and-architecture
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–
1.5k
views
1
answers
2
votes
pipelining
Consider a non-pipelined processor design which has a cycle time of 10ns and average CPI of 1.6. If each pipeline stage adds extra 20ps due to register setup delay ... cycles (these occurrences are disjoint). What is the new CPI ?(ans=2.05)
Satbir
1.5k
views
Satbir
asked
Dec 7, 2018
CO and Architecture
pipelining
co-and-architecture
clock-cycles
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–
2.1k
views
2
answers
2
votes
Pipelining
Na462
2.1k
views
Na462
asked
Nov 7, 2018
CO and Architecture
pipelining
co-and-architecture
clock-cycles
+
–
3.9k
views
1
answers
0
votes
Computer organization
How many cycles are required for a 100 MHz processor to execute a program which requires 5 seconds of CPU time?(a) 10^9 cycles (b) 50 × 10^7 cycles (c) 10^8 cycles (d) 50 cyclesSolution: Option (b)
sahil_malik
3.9k
views
sahil_malik
asked
Oct 10, 2018
CO and Architecture
co-and-architecture
clock-cycles
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–
395
views
0
answers
0
votes
ME test series
newdreamz a1-z0
395
views
newdreamz a1-z0
asked
Oct 7, 2018
CO and Architecture
co-and-architecture
machine-instruction
operand-forwarding
clock-cycles
numerical-answers
made-easy-test-series
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–
1.7k
views
1
answers
3
votes
Minimum clock cycle
Na462
1.7k
views
Na462
asked
Sep 24, 2018
CO and Architecture
co-and-architecture
pipelining
clock-cycles
numerical-answers
+
–
255
views
0
answers
0
votes
Computer organisation- DMA
sidlewis
255
views
sidlewis
asked
Sep 12, 2018
CO and Architecture
co-and-architecture
cache-memory
array
clock-cycles
+
–
1.6k
views
1
answers
0
votes
Pipelining
To execute an instruction by a 32-bit machine the following steps are carried out: Fetch, Decode,Execution, Memory access and Store, each of which ... an equivalent non pipeline processing system is ________.Ans. 4.8Please Explain Briefly
Na462
1.6k
views
Na462
asked
Jul 21, 2018
CO and Architecture
pipelining
co-and-architecture
speedup
clock-cycles
+
–
1.2k
views
1
answers
1
votes
Addressing mode
Prateek Raghuvanshi
1.2k
views
Prateek Raghuvanshi
asked
May 27, 2018
CO and Architecture
addressing-modes
clock-cycles
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–
422
views
1
answers
1
votes
made easy test series
rohit vishkarma
422
views
rohit vishkarma
asked
Jan 4, 2018
Digital Logic
combinational-circuit
clock-cycles
+
–
612
views
1
answers
2
votes
Pipelining
Parshu gate
612
views
Parshu gate
asked
Nov 29, 2017
CO and Architecture
pipelining
co-and-architecture
clock-cycles
speedup
+
–
1.5k
views
1
answers
2
votes
Pipelining Problem
How to slove this type of problems? How to understand the problem?Please help me out. Given answer is 31
Parshu gate
1.5k
views
Parshu gate
asked
Nov 18, 2017
CO and Architecture
pipelining
co-and-architecture
clock-cycles
+
–
1.4k
views
1
answers
4
votes
Test question on Pipelining
Parshu gate
1.4k
views
Parshu gate
asked
Nov 3, 2017
CO and Architecture
co-and-architecture
pipelining
clock-cycles
+
–
256
views
1
answers
0
votes
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 19
In an $8$ segment pipeline, the total number of clock pulses that process $150$ tasks are ______ cycles.
Bikram
256
views
Bikram
asked
Nov 25, 2016
CO and Architecture
tbb-coa-1
co-and-architecture
numerical-answers
clock-cycles
+
–
436
views
1
answers
1
votes
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 2
In a seven-segment pipeline, each segment takes $1$ cycle. Assuming there are no stalls, the number of clock cycles required to process $180$ tasks in a seven – segment pipeline is _______ cycles.
Bikram
436
views
Bikram
asked
Nov 25, 2016
CO and Architecture
tbb-coa-1
co-and-architecture
numerical-answers
pipelining
clock-cycles
+
–
12.7k
views
2
answers
6
votes
Q26 ch-5 M_E workbook
suppose that in 1000 memory reference there are 40 misses in the first level cache and 20 misses in the second level cache. Assume miss penalty from the L2 ... (miss penalty)right??so which miss rate and miss penalty should i put here?
khushtak
12.7k
views
khushtak
asked
Oct 27, 2015
CO and Architecture
co-and-architecture
cache-memory
clock-frequency
clock-cycles
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