suppose that in 1000 memory reference there are 40 misses in the first level cache and 20 misses in the second level cache. Assume miss penalty from the L2 cache to memory is 100 cycles the hit time of the L2 cache is 10 clock cycles.the hit time of the L1 cache is 1 clock cycle.
Ques. if there are 1.5 memory references per instruction. What is the average stall cycles per instruction
a. 3.4 cycles b. 3.5 cycles c. 3.2 cycles d. 3.6 cycles
My work-
miss rate of L2 is 0.02 (global) and 0.5(local)
miss rate for L1 is 0.04
miss penalty for L1 is 60 cycles
for average stall cycles per instruction = (memory reference per instruction) x (miss rate) x (miss penalty)
right??
so which miss rate and miss penalty should i put here?