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Recent questions tagged memory-management

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NIELIT 2018-38
Find the effective access time for the memory for the given data.Page fault service time $=8$ msAverage memory access time $=20$ nsOne page fault is generated for every memory access $=10^6$29$ ns$33$ ns$28$ ns$30$ ns
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MadeEasy Test Series: Operating System - Memory Management
Consider a paging scheme, in which average process size is 32MB and each page table entry size is 4B. The optimal size of page to minimize the total overload due to page table and internal fragmentation is _______KB.
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GA Testseries
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MadeEasy Workbook: Operating System - Memory Management
Consider the following sequence:Process P1 of size 7k loadedProcess P2 of size 4k loadedProcess P1 is terminated and space is returnedProcess P3 of size 3k loadedProcess P4 of size ... ? (Assume frame size is 1K).A 1K B 2K C 3K D NONE
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Bit Map
A bit-map can be used to keep track of which blocks are free in a file-system’s partition on disk.Assuming, 1 KB block size and a disk size of 40 GB, what is the size of the bit map?
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threads
There is no protection between the threads of same process why ?
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Internal and External fragmentation
Consider $6$ memory partitions of sizes $200$ $\text{KB}$, $400$ $\text{KB}$, $600$ $\text{KB}$, $500$ $\text{KB}$, $300$ ... memory slots and the process size whose size must be greater than Max free slot size.Someone verify it.
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Made easy
Option (a) Best fit (b) Next fit (c) First fit
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Multilevel paging
Consider a machine with byte addressable memory 32 bits virtual addresses, 32 bits physical addresses and 4 KB page size. If a two-level page table system is used ... table & 2nd level page table(s) ? Also how to calculate memory overhead?
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doubt
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Paging - Memory management
Why do we need multilevel paging?According to me the reason is that page table needs contiguous memory allocation.So if page table size is too large, we may ... we store all levels page table in memory or only the outer level page table?
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AceBook
Consider the machine with 64 MB Physical Memory and a 34 bit Virtual Address Space. If the page size is 4KB, the appropriate sizes of conventional and inverted page table sizes ... 16Kd)16K, 4M.soln: is Option C. but my ans is (7MB, 28KB)
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Acebook
For a page size of 200 words, what is the page number and offset for a logical address of 1142.a)5,142b)2,142c)6,142d)7,140
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AN INTRODUCTION TO OPERATING SYSTEMS CONCEPTS AND PRACTICE (GNU/LINUX)
Suppose UNIX disk block will hold 2048 disk addresses. What is the maximum sizedfile using only the direct pointers? Single-indirection capability? Double indirectioncapability? Triple-indirection capability?
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Process Management
Q.Consider the processes P1, P2, P3, P4 whose arrival times are 0, 1, 2, 3 and Burst times are 5, 2, 13, 7. If the Context Switching time is 1 unit (ms), what is ... Job Next scheduling algorithm is used? (a) 7.5 (b) 6.25 (c) 6.5 (d) None
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Memory Management
Dynamically Linked Libraries imply more page faults than static? Why?
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Operating Systems - Memory Allocation
Is it true that we can allocate only one process to one block?In First fit memory allocation scheme, can we allocate two processes to the same block of memory if block has the capacity to accommodate both of them?
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Virtual Memory
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Multi-level paging doubt
Consider a computer system using 2-level paging with TLB. The logical address supported is 32 bits. The page table is divided into 512 pages each of size ... $544KB$Is my analysis correct?Below is the visualisation what I see is happening.
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Multilevel Paging
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Virtual address space
A one-to-one mapping of the entire physical address space to a process's virtual address space is a correct address translation solution. True/False. Explain.
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Page Table
A page table based translation will always consume less memory to store translation meta-data, than a seg-mentation based solution. True/False. Explain.
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Memory Management : paging
Consider a system using 2 level paging applicable page table is devided into 2k pages each size 4kB. If PAS is 64 MB which is devided into 16K frames . PTE size ... the levels calculate the length of PA, LA and # of entry at second level?
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Operating System Multilevel Paging
In a 32-bit machine we subdivide the virtual address into 4 segments as follows: 10-bi 8-bit 6-bit 8 bit We use a 3-level page table, such ... page cannot fit in one page tableBut outermost page table should fit in one page ??ref:
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William stalling :Memory Management
Suppose :TLB lookup time = 20 nsTLB HIT ratio = 80%Memory access time = 75 nsSwap page time = 500000 ns50% pages are dirty and os uses a single level page ... assume cost to update TLB , page table , frame table is negligible (if needed).
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Galvin operating system
CPU generates logical address and that logical address is converted to physical address.What does this means exactly ??Assume run time binding is used.When process ... to get some data/instruction from memory right ?Please help me in this
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#OS Dynamic linking and Dynamic Libraries?
Please explain Dynamic linking and Dynamic Libraries in an intuitive way with an example.
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#Galvin Memory Management Self Doubt.
In Galvin 9th edition or even in 8th editionin Chapter 8,topic- 8.1.2 Address BindingIt's given the linkage editor or loader in turn binds the ... relocatable addresses to absolute addresses? So, how come they're saying loader?Thanks!
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MadeEasy Test Series: Operating System - Memory Management
Consider five memory partitions of size 100 KB, 500 KB, 200 KB, 450 KB and 600 KB in same order. If sequence of requests for blocks of size 212 KB, 417 KB, ... A) BEST FITB) FIRST FITC) NEXT FITD) BOTH NEXT FIT AND BEST FIT RESULTS IN SAME
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Galvin, Virtual memory exercise 9.15
A simplified view of thread states is Ready, Running, andBlocked, where a thread is either ready andwaiting to be scheduled, is running on the processor, or is blocked ... . However, I am highly confused over answers to part b, and part c.
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