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Recent questions tagged memory-management

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Galvin Edition 9 Exercise 8 Question 13 (Page No. 391)
Compare the memory organization schemes of contiguous memory allocation, pure segmentation, and pure paging with respect to the following issues:$a$. External ... $b$. Internal fragmentation$c$. Ability to share code across processes
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Galvin Edition 9 Exercise 8 Question 12 (Page No. 391)
Most systems allow a program to allocate more memory to its address space during execution. Allocation of data in the heap segments of programs is an example of ... ?$a$. Contiguous memory allocation$b$. Pure segmentation$c$. Pure paging
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Galvin Edition 9 Exercise 8 Question 11 (Page No. 391)
Given six memory partitions of $300$ $KB$, $600$ $KB$, $350$ $KB$, $200$ $KB$, $750$ KB$ and $125$KB$ (in order), how would the $first-fit$, ... and $375$ $KB$ (in order) ? Rank the algorithms in terms of how efficiently they use memory.
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Galvin Edition 9 Exercise 8 Question 10 (Page No. 391)
Consider the following process for generating binaries. A compiler is used to generate the object code for individual modules, and a linkage editor is used ... linkage editor to facilitate the memory-binding tasks of the linkage editor ?
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Galvin Edition 9 Exercise 8 Question 9 (Page No. 391)
Explain the difference between internal and external fragmentation.
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Galvin Edition 9 Exercise 8 Question 8 (Page No. 390-391)
In the IBM/370, memory protection is provided through the use of keys. A key is a 4-bit quantity. Each 2-K block of memory has a key (the ... of processes$d$. Multiprogramming with a variable number of processes$e$. Paging$f$.Segmentation
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Galvin Edition 9 Exercise 8 Question 7 (Page No. 390)
Sharing segments among processes without requiring that they have the same segment number is possible in a dynamically linked segmentation system.a. Define a system ... to be shared without requiring that the page numbers be the same.
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Galvin Edition 9 Exercise 8 Question 6 (Page No. 390)
Describe a mechanism by which one segment could belong to the address space of two different processes.
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Galvin Edition 9 Exercise 8 Question 5 (Page No. 390)
What is the effect of allowing two entries in a page table to point to the same page frame in memory? Explain how this effect could be used to decrease the ... What effect would updating some byte on the one page have on the other page ?
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Galvin Edition 9 Exercise 8 Question 4 (Page No. 390)
Consider a logical address space of $64$ pages of $1,024$ words each, mapped onto a physical memory of $32$ frames.$a$. How many bits are there in the logical address ?$b$. How many bits are there in the physical address ?
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Galvin Edition 9 Exercise 8 Question 3 (Page No. 390)
Why are page sizes always powers of 2 ?
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Galvin Edition 9 Exercise 8 Question 2 (Page No. 390)
Consider a system in which a program can be separated into two parts: code and data. The $CPU$ knows whether it wants an instruction (instruction ... be shared among different users. Discuss the advantages and disadvantages of this scheme.
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Galvin Edition 9 Exercise 8 Question 1 (Page No. 390)
Name two differences between logical and physical addresses.
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Virtual Memory
The minimum number of page frames that must be allocated to a running process in a virtual memory environment is determined byInstruction Set Architecturepage sizephysical ... above question is ISA ??Please explain the concept behind it
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MadeEasy Subject Test 2019: Operating System - Memory Management
Please explain it with solution or concept.
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Applied Course | Mock GATE | Test 1 | Question: 49
How much memory is used for page tables, when there are $10$ process running in the system with the below details?Virtual Address space: $1GB$Page size: $1KB$Each page table ... of $2^{14}$ physical pages.$10$ MB$20$ MB$30$ MBNone of these
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Paging and virtual memory
If there is 2 or more level paging for processes, is it possible to have more than 1 page fault while accessing any single addressable unit(byte or word) ?
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UPPCL AE 2018:61
Consider a computer system with $32-$ bit virtual addressing and page size of sixty-four kilobytes. The computer system has one-level page table per process with each ... $None of the above$7$5$
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UPPCL AE 2018:57
Consider the following $\text{C}$ function executed in an $\text{OS}$ with paging where the page size is $4$ ... $ misses during the execution of the for loop?$2048$2$0$1$
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UPPCL AE 2018:21
Assume a memory access to main memory on a cache miss takes $30 \; \text{ns}$ and a memory access to the cache (on a cache hit ) takes $3 \; \text{ns}.$ If $80 \%$ ... $9 \text{ns}$4.4 \text{ns}$2.2 \text{ns}$
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Relation between physical address, logical address and relocation register
Physical address is(A) The logical address added by the value in re-locatable registers(B) Re location register – logical address(C) Re location address + relocation register(D) None of these
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GATE Overflow | Mock GATE | Test 1 | Question: 18
Assume a program has just referenced an address in virtual memory. Which of the following scenario cannot occur?TLB miss with no page faultTLB hit and page replacementTLB miss and page faultTLB hit with no page fault
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GATE Overflow | Mock GATE | Test 1 | Question: 19
A computer system consists of infinitely large primary memory storage capacity. In other words the physical address space exceeds the logical address ... memory concept can be used to give multiprogramming capability to system
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GATE Overflow | Mock GATE | Test 1 | Question: 38
Consider a system with paging-based memory management, whose architecture allows for a $4\text{GB}$ virtual address space for processes. The size of logical pages and physical frames is ... text{GB} + 4 \text{KB}$4 \text{MB} + 4 \text{GB}$
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MadeEasy Test Series: Operating System - Memory Management
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MadeEasy Test Series: Operating System - Memory Management
Consider five memory partitions of size $100 \text{ KB }, 500 \text{ KB }, 200 \text{ KB }, 450 \text{ KB and } 600 \text{ KB }$ in same order. If ... in sameNone of the above Answer given by ME: Option $(B)$My answer: Option $(D)$
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Multi-level paging-doubt
Consider a system which has 2 level paging.The page table is divided into 2K pages and each page is having 4K entries.Memory is word addressable and Physical address ... or I am poor at multi-level paging?(Please tell where I went wrong)
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madeeasy OS 2019- Memory overhead multilevel paging
for memory overhead in Multi level paging, for innermost table only 1 page size shall be counted na? and NOT the complete page table size?please explain the concept, thanks!
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multilevel paging
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