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Recent questions tagged memory-interfacing

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Made Easy Test Series 2024
A dynamic RAM has a refresh cycle of 32 times per msec. Each refresh operation requires $100$ nanosecond and a memory cycle requires $200$ nanosecond. What percentage of memory's total operating time is required for refreshes?
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GATE CSE 2023 | Question: 32
A $4$ kilobyte $\text{(KB)}$ byte-addressable memory is realized using four $1 \mathrm{~KB}$ memory blocks. Two input address lines $\text{(IA4 and IA3)}$ are connected to the chip ... (0,1,2,3)$(0,1024,2048,3072)$(0,8,16,24)$(0,0,0,0)$
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The number of address lines required to address 8 GB memory is a) 8 b) 1024 c) 32 d) 33 . Please help
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prepladder question bank
How many 128 K × 1 RAM chips are required, and what is the size of decoder needed to give the memory capacity of 1 MB. Here memory is byte addressable.
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Computer Architecture and Organisation
1. Assume a Bus System constructed to connect 7 registers and memory unit of 32 word length using multiplexer. So:a) How many multiplexer is needed?b) What ... .e size of multiplexer?c) Describe decoder used to select address of memory unit
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NIELIT Scientific Assistant A 2020 November: 55
A $26-$bit address bus has maximum accessible memory capacity of ________$\text{64 MB}$\text{16 MB}$\text{1 GB}$\text{4 GB}$
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NIELIT 2016 DEC Scientist B (IT) - Section B: 37
How many address lines are needed to address each memory location in a $2048\times4$ memory chip?$10$11$8$12$
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NIELIT 2016 DEC Scientist B (CS) - Section B: 58
CPU consists of _______.ALU and Control UnitALU, Control Unit and MonitorALU, Control Unit and Hard diskALU, Control Unit and Register
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NIELIT 2017 July Scientist B (CS) - Section B: 27
Which memory is difficult to interface with processor?Static memoryDynamic memoryROMNone of the option
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NIELIT 2017 July Scientist B (CS) - Section B: 28
For a memory system, the cycle time isSame as the access time.Longer than the access time.Shorter than the access time.Multiple of the access time.
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NIELIT 2017 July Scientist B (CS) - Section B: 29
In comparison with static RAM memory, the dynamic RAM memory hasLower bit density and higher power consumptionHigher bit density and lower power consumptionLower bit density and lower power consumptionNone of the option
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NIELIT 2017 July Scientist B (CS) - Section B: 30
If each address space represents one byte of storage space, how many address lines are needed to access RAM chips arranged in a $4\times 6$ array, where each chip is $8K\times 4$ bits?$13$14$16$17$
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NIELIT 2017 DEC Scientist B - Section B: 28
A RAM chip has $7$ address lines, $8$ data lines and $2$ chips select lines. Then the number of memory locations is __________$2^{12}$2^{10}$2^{19}$2^{13}$
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No of chips
A memory system of size 16 kbytes is required to be designed using memory chips which have 12 address lines and 4 data lines each.No of chips required to design the memory system ______.Please provide a detailed solution.
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GATE CSE 2019 | Question: 2
The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system has $16$ ... by the chip select (CS) signal?C800 to CFFFCA00 to CAFFC800 to C8FFDA00 to DFFF
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ACE(COMPUTER ORGANIZATION)
Q.1 A 32 bit wide main memory unit with a capacity of 4GB is built using 128M *8 bit DRAM .the number of rows of memory cells in the DRAM chip is ... of time require to refresh the 4GB DRAM is ..?Ans-81.92 microsec.explanation ????
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MadeEasy Test Series: CO & Architecture - Memory Interfacing
Consider a DRAM that must be given a refresh cycle $64$ times per msec. Each refresh operation requires $100 \ nsec$ ... total operating time must be given to refresh is _______ (upto $2$ decimal places)
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Self doubt on Memory Interfacing 2
A computer uses RAM Chips of 512X8 and ROM Chips of 2048x8. The computer needs 2K Bytes of RAM, 4K Bytes of ROM, and 4 interface units each with 4 ... Mapped I/O configuration is used. How many RAM Chips and ROM Chips are required?
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Self doubt on Memory Interfaacing
A computer uses RAM Chips of 512X8 and ROM Chips of 2048x8. The computer needs 2K Bytes of RAM, 4K Bytes of ROM and 4 interface units each with 4 registers ... mapped I/O configuration is used. How many RAM Chips and ROM Chips are required?
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