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Recent questions tagged decoder

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Counting number of "AND" and "OR" gates in a multiplexer and decoder. How do we approach such questions?
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Madeeasy ots Digital Logic Combinational Circuits
I am confused in active low enable input and active low output?
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ISI2020-PCB-CS: 10
Suppose instead of a decoder with $n$ input bits ( $n$ is even) to access a memory of size $2^{n}$, one uses two decoders of input sizes $k$ ... the time complexity of the decoder is measured by the number of output lines of that decoder.
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ISI2021-PCB-C10
Suppose instead of a decoder with n input bits (n is even) to access a memory of size 2^n, one uses two decoders of input sizes k bits and (n-k ... time complexity of the decoder is measured by the number of output lines of that decoder.
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Made Easy Test Series
A 3 to 8 decoder is shown below:All output lines of decoder will be high when all the input I1, I2, I3 are;are high and G1 , G2 are loware high and ... behind this question. Why we have to disable the Decoder to make all the outputs high ?
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3 to 8 line Decoder (Combinational Circuit)
If F1 = ∑m(1,2,4,7) and F2 = ∑m(3,5,6,7), implement them using 3 to 8 line decoder. Comment on their logic operations.
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GATE CSE 2020 | Question: 20
If there are $m$ input lines and $n$ output lines for a decoder that is used to uniquely address a byte addressable $1$ KB RAM, then the minimum value of $m+n$ is ________ .
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Made Easy Test Series: Digital Logic
A $3\times 8$ decoder with $2$ enable inputs is used to address $8$ block of memory. What will be the size of each memory block when addressed from a $16$ bit bus with $2$ MSB’s used to enable the decoder?
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Morris Mano Edition 3 Exercise 5 Question 18 (Page No. 199)
Construct a $5 \times 32 $ decoder with four $3\times8$ decoders with enable and one $ 2 \times 4$ decoder. use a block diagram also.
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Morris Mano Edition 3 Exercise 5 Question 17 (Page No. 199)
Draw the logic diagram of a 2-to-4 line decoder with only NOR gates. Include an Enable input.
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DRDO 2009
The number of 2-to-4 line decoders with enable input needed to construct a 4-to-16 line decoder are?
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Made easy theory book
Solve this.
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MadeEasy Test Series: Digital Logic - Decoder
A $3 \times 8$ decoder with two enables inputs is to be used to address 8 blocks of memory. What will be the size of each memory block when addressed from a ... two enable inputs is to be used mean? I am not able to visualize the circuit.
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NIELIT 2018-39
A RAM chip has a capacity of $1024$ words of $8$ bits each $(1K \times 8)$. The number of $2 \times 4$ decoders with enable line needed to construct a $32 K \times 8$ RAM from $1K \times 8$ RAM is$4$5$6$7$
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Decoder
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