→ The capacity of the RAM needed = 16K
→ Capacity of the chips available = 1K
→ No. of address lines = 16K/1K = 16
→ Hence we can use 4×16 decoder for this. But we were only given 2×4 decoders.
→ So, 4 decoders are required in inner level as from one 2×4 decoder we have only 4 output lines whereas we need 16 output lines.
→ To point to these 4 decoders, another 2×4 decoder is required in the outer level.
→ Hence no. of 2×4 decoders to realize the above implementation of RAM = 1+4 = 5