Andrew S. Tanenbaum (OS) Edition 4 Exercise 3 Question 16 (Page No. 255)

Question

You are given the following data about a virtual memory system:

1. The $TLB$ can hold $1024$ entries and can be accessed in $1$ clock cycle $(1\: nsec).$ 
2. A page table entry can be found in $100$ clock cycles or $100\: nsec.$ 
3. The average page replacement time is $6\: msec.$

If page references are handled by the $TLB\:\: 99\%$ of the time, and only $0.01\%$ lead to a page fault, what is the effective address-translation time?

Answer 1

The question is asking about only effective address-translation time i.e time required to calculate physical address of the page in main memory.

$\therefore$ Effective address-translation time = $0.99(1) + 0.01(0.99(1+100) + 0.01(1+100+6000000))=602ns$

Answer 2

$0.99(1+100)$+   $0.01(1+100+ 0.01(100+6000000))$ $ns$

$=702$ $ns$

Comments

as they are asking for effective address translation time, whats was the need accessing memory in TLB hit?

---

Yes you are right. No need for extra memory acces in TLB as TLB already contains address of the frame.

You can see my answer https://gateoverflow.in/324655/andrew-tanenbaum-os-edition-exercise-question-16-page-no-255?show=415103#a415103

---

yup, i am also getting the same 601.98 ns.