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Recent questions tagged co-and-architecture

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#COA #CacheMemory
What is the default access method of Cache Memory? Simultaneous or Hierarchical?
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Addressing Modes
When we write MOV #1000 , it means we are writing the value 1000 into the accumulator. But when we write MOV 1000 here 1000 refers to address of what ? register or MM ? (knowing that MOV works only between registers).
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cache miss question
In $T_{Read Avg}$, shouldn’t it be $T_{Read Avg}$ = (10*0.9) + 0.1*(10+100), because it must be checking the cache in case of cache miss too, right?
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Difference b/w cache & TLB
What is the difference b/w cache & TLB? TLB is stored in cache too right? TLB helps in addressing like a faster version of page table while speaking of cache, it directly stores the process page directly right?
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PERSONAL DOUBT [PIPELINING]
So I know pipelining has 5 stages: IF, ID, EX, MA, WB.Now the question is if I have a program of few instruction which has both ALU operation and LOAD/ ... the 5 stages how many stages will be reqiured for ALU and how many for LOAD/STORE.
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Arihant Gate Tutor
If a processor has 32-bit virtual address, 28-bit physical address, 2 kb pages. How many bits are required for the virtual, physical page number?17, 2121, 176, 10NoneThe answer given is b. 21, 17
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Arihant Gate Tutor
Which of the following processor registers are used for fetch and execute operations ?Program CounterInstruction RegisterAddress RegisterOptions :a and bb and ca and cNone of these
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Arihant Gate Tutor
Memory mapping table is used to(a) Translate virtual address to physical address(b) Translate physical address to virtual address(c) Both(d) None
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Calcutta University Question Paper
(a) Corresponding to the following reservation table, draw the state diagram. Clearly indicate the collision vectors, collision matrices, state transition diagram, and MALS 01234S1AB ABS2 A A S3B AB A
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