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Recent questions tagged co-and-architecture

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scientist B cpcb exam 2023. computer-science engineering. Need help to solved! Urgent!
We have a combinational block [implementing an operation] that can be divided into 3 partitions as 70ps, 40ps and 65ps. The system throughput can be ... maximum achievable throughput (in GOPS, rounded to 2 decimal places) is _____________.
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Topic: Hit Ratio
The access time of a main memory is 800 ns and cache memory access time is 70 ns. The ratio of read and write requests is 7:3. The hit ratio for read ... e. both read and write requests) if a write-through policy is used for cache updation.
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Ace Test Series | Computer Organistaion
A pipelined processor with a separate instruction & data cache has 5- stages, the cycle time 30 nano sec. It can start a new instruction on every cycle when there were ... is the throughout of CPU.a) 31 MIPSb) 24 MIPSc) 48 MIPSd) 10 MIPS
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Addressing mode
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Addressing Modes
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Cache Mapping
In a 2 level hierarchy, the cache has an access time of 15 ns and the main memory has an access time of 110 ns, the hit rate of the cache is 90%. ... size of the cache is 16 Bytes, then average memory access time including miss penalty is?
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Computer Organization
Under what category does Universal Serial Bus fall: System Bus or a Network connection or something else?
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Synchronization problem on single processor cpu
Consider the following multi threaded code.volatile static int flag1= 0, flag2= 0; // code for thread 1 (or T1) flag1 = 1; if (flag2==0) code1(); // ... be invoked!Also, what will be the answer if we remove the volatile type from the flags.
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Computer Architecture Cache, VM, and DRAM
A byte-addressable system with 16-bit addresses ships with a three-way set associative, write-back cache (i.e., each block needs a dirty bit). The cache implements ... aside from the tag itself, each block needs 1 valid bit, 1 dirty bit).
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when CPU needs to access some data does it first check in registers or L1 cache?
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coa question
Interpret the main memory addresses FF010,12364,andC7691 considering direct, associative and 2 way set associative mapping if the main memory size is 1MB,word size is 16 bytes, and cache size is 64KB.
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BARC 2015
Operand is fetched from memory During(A) fetch phase(B) execute phase(C) decode phase(D) read phase
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self doubt
Can Interrupt-Driven I/O be memory mapped?Polling is memory mapped or IO mapped?
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With the help of the following information, determine the size of the sub-fields (in bits) in the address for direct mapping, associative mapping and set-associative mapping:  512 MB main memory and 2 MB cache memory  Address space of the processor is 256 MB  The block size is 256 bytes  There are 16 blocks in a cache set.
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self doubt
true/ falsecpu generate logical address(which is for Rom/secondary memory) and MAR stores physical address which is (data/instruction ready for execution in ram)
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GATE CSE 2023 | Question: 23
Consider a $3$-stage pipelined processor having a delay of $10 \mathrm{~ns}$ (nanoseconds), $20 \mathrm{~ns}$, and $14 \mathrm{~ns},$ for ... execution time for executing $100$ instructions on this processor is _____________ $\mathrm{ns}.$
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GATE CSE 2023 | Question: 24
A keyboard connected to a computer is used at a rate of $1$ keystroke per second. The computer system polls the keyboard every $10 \mathrm{~ms}$ (milli seconds) ... is _____________. (Rounded off to one decimal place)
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