GATE CSE 2008 | Question: 38

Question

In an instruction execution pipeline, the earliest that the data TLB (Translation Lookaside Buffer) can be accessed is:

• A. before effective address calculation has started

• B. during effective address calculation

• C. after effective address calculation has completed

• D. after data cache lookup has completed

Comments

In a system without virtual memory , the EA will be either a main memory address or a register.

In a virtual memory system , the EA is a virtual address or a register.

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TLB stores only page table of large size program(Programs which are unable to fit in main memory). so after effective address calculation the given address will be reached using help of the page table of that program stored in TLB. Since virtual program is large in size so page table is also large & do not get fit in one page so multi-level paging. TLB decreases the access time to search in multi-level page table because it provides superfast memory access.

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Nitesh Singh 2

TLB stores only page table of large size program(Programs which are unable to fit in main memory)

i think you mean “virtual memory” here instead of TLB. 

Answer 1

C is the answer here.

Effective address is the address after applying the addressing mode like indexed, immediate etc. But this resulting address is still the virtual address, the physical address is invisible to the CPU and will be given only by the MMU when given the corresponding virtual address. Virtual address is given for TLB look up. TLB -Translation Lookaside Buffer, here Lookaside means during Address translation (from Virtual to Physical). But virtual address must be there before we look into TLB.

https://gateoverflow.in/?qa=blob&qa_blobid=15279338060050073946

Comments

What is meant by Effective address here? This q is doubtful for me. Thanks to @hetgate23 who pinged it. 

Maybe Option B or Option C

4 opinions:-
1) If effective address is the one that is received after what we know as effective address calculation, then in indirect addressing mode, yes it can be accessed even during EA Calculation is Done. So $Option B$

2) If EA is the Virtual address being spoken about, then it will be $Option C$, because using the Virtual address we get the EA and then we access tlb and get the frame no.

3) $Option D$ can't be the answer because which one will be accessed first cache or tlb is implementation dependent whether its Physically accessed cache, or virtually accessed cache.

4) $Option A$ also doesn't feel right because we actually want to calculate the effective address. So first we must start the calculation then we need to lookup tlb/cache as reqd.

@Pranavpurkar @ankitgupta.1729 Sir, @Argharupa Adhikary Aditya_ You all might wanna look.

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@Abhrajyoti00

if the system doesn’t contains TLB i.e the system without virtual memory then this question is also not correct.

But they have specifically mentioned TLB ,  thus first it will generate the virtual address and then to convert into physical address , it will lookup TLB first to get the desired frame in memory. So, here the virtual address is nothing but the effective address(address of target) which is then converted to physical address after TLB lookup. 

so, option C seems correct.

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@Arjun sir, but during the IF fetch we are already reading instructions from memory with the help of the address from the program counter. If we use paging along with virtual address space, don't we have to perform a TLB lookup for reading instructions?

Answer 2

C as only after the calculation of Virtual address you can look up in the TLB

Answer 3

in case of indirect addressing mode.the flow will  be 

 [data from address field ] -> memory access-> TLB ->actual frame address ->data in that memory location -> back to processor->now this data is my effective address.

sir,so i think answer should be B.

Comments

Answer: (B) 

Explanation: When we calculate effective address, first of all we access TLB to access the Frame number.

Logical address generated by CPU breaks in two parts : page number and page offset, for faster accessing of data we place some page table entries in a small hardware TLB whose access time is same as cache memory. So initially when page no. is mapped to find the corresponding frame no., first it is look up in TLB and then in page-table (in case if TLB miss).

During effective address calculation TLB is accessed.

So (B) is correct option.

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seems correct!  but not satisfied with the explanation.

@Bikram sir  please clear this thing !

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Question says data TLB

Answer 4

B. During effective address calculation