https://gateoverflow.in/753/gate2001-12?show=279851#c279851

Question

doubt in this gate question- https://gateoverflow.in/753/gate2001-12?show=279851#c279851

In instruction I3 how is it getting the value of r2 which is computed in I1 instruction?? Can memory access stage read the value of updated register values of write back stage??

please resolve my doubt.

Comments

Got your doubt..not sure whether my reasoning is valid or not..but I have read somewhere that MUX can be used before accessing a data item in a particular stage. It will have 2 i/p lines, one with new other with old value of register. The select line will select the new i/p line if any change is made to registers that will be used by this stage.

For eg in this case, R2 will be used by MEM stage of I3. As R2 is already decoded at clock 4 so I3 will be knowing the old value of R2 and I1 updates R2 at clock 5 which will be unknown to I3. Here the MUX is used which has Decoded R2 value in the old i/p line and the latest R2 value updated by I1 in its WB stage in the new i/p line. The CU will now select the new line when it sees R2 has been changed recently.

I don't know how the circuitry works here. Correct me anywhere you feel its wrong :/

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it makes sense and this is a logical way to get the updated values. Thanks because without assuming this 8 clock cycles is impossible. I hope they also mean the same.