Option C is correct.
Speedup=Time taken by Non-pipeling/Time taken by pipeling
= nKT/(K+(n-1))T = nK/(K+(n-1)),
where n is no of instructions,
K is no of stages,
T is time period of each clock cycle
When n >>K , K+(n-1) ~=n
and Speedup=nK/n=K
So, max Speedup is equal to no of stages. Hence S1 is wrong and S2 is correct.
S3- Branch prediction is a method to predict which branch is to be taken on the basis of past instructions, as in case of a loop which runs 100 times you can predict that for some 100 steps, control of instructions will jump around the loop only.This is done to avoid Control Hazard and nothing to do with Data hazard. Hence False.
S4- WAW(Write after write) hazard is when-
I1: ADD R1, R2, R3
I2: SUB R1, R4, R5
I1 is restricting I2 from writing to R1, so we rename R1 in I2 as R6 to allow parallel execution
I1: ADD R1, R2, R3
I2: SUB R6, R4, R5
Similarly, WAR hazards can also be removed using Register renaming. Hence true.
S5- Stalls are introduced to restrict instruction's execution while it is waiting for the o/p of another instruction.So, stalls are decreasing the performance of the system by not utilizing that clock cycle in which the instruction was waiting.Hence false.
S6- Structural hazards are a result of insufficient resource availability for pipelined execution of instructions.eg-if there is a single memory for Instructions(Programs) and Data then Instruction Fetch stage and Write data to memory stage cant execute in parallel for two different instructions.To avoid this separate memory module are introduced.Hence true.
